The present invention relates to the field of integrated circuits, and more particularly to architectures for programmable logic integrated circuits.
Programmable logic integrated circuits are well known to those in the electronic art. Such programmable logic integrated circuits are commonly referred as PALs (Programmable Array Logic), PLAs (Programmable Logic Arrays), FPLAs (Field Programmable Logic Arrays), PLDs (Programmable Logic Devices), EPLDs (Erasable Programmable Logic Devices), CPLDs (Complex Programmable Logic Devices) EEPLDs (Electrically Erasable Programmable Logic Devices), LCAs (Logic Cell Arrays), FPGAs (Field Programmable Gate Arrays), and the like. Such devices are used in a wide array of applications where it is desirable to program standard, off-the-shelf devices for specific applications. Such devices include, for example, the well-known Classic™, MAX®, and FLEX® families of EPLDs manufactured by Altera Corp.
The popular FLEX® PLD architecture from Altera Corp. includes many logic array blocks (LABs) arranged in a two-dimensional array and multiple embedded array blocks (EABs). This PLD architecture further includes two arrays of intersecting signal conductors for programmably selecting and conducting logic signals to, from, and between the LABs, the EABs, and the device I/O pins. Each LAB includes a number of programmable logic elements (LEs) that provide relatively elementary logic functions such as NAND, NOR, exclusive OR, flip flops, and other functions. The LABs are generally used to implement general logic and the EABs are generally used to implement memory and specialized logic functions.
A user configures a programmable logic integrated circuit, such as a PLD or a FPGA, to implement the desired logical functions. For example, the user may configure a PLD to be a microcontroller, a microprocessor, a multiplier, a digital filter, or the like. During the design phase, due to circumstances such as errors in the design or changes in requirements, the user may need to modify the design by reconfiguring the PLD. Once a particular design for the PLD has been successfully implemented and tested, the design typically does not need to be changed again. At that point, it may be desirable to reduce production costs by implementing the design in a lower cost device such as a mask-programmable PLD (MPLD).
A MPLD is a device that is configured or “hard-wired” during the fabrication of the device. For example, the PLD manufacturer fabricates a MPLD design by using a specific metal mask corresponding to the user's design. Conventionally, the conversion from a programmable design into a MPLD design is time consuming and inefficient. These design hurdles are contrary to the low cost and fast time to market requirements of many electronics products. As can be seen, techniques for efficient conversion of a design from a programmable design to a MPLD design is highly desirable. Further, it is important that the MPLD provides the available functionality of the programmable design it replaces.